1. Field of the Invention
The present invention relates to a CDMA synchronous acquisition circuit of a receiver using a spread spectrum communication system based on CDMA (Code Division Multiple Access), and particularly to a CDMA synchronous acquisition circuit of a CDMA receiver which is used in a mobile communication system.
2. Description of the Related Art
According to the CDMA communication system, transmission data are transmitted while subjected to spread-spectrum processing by using spread codes at a transmitter, and the transmission data thus transmitted are subjected to inverse spread-spectrum processing by using the replica of the spread codes at a receiver, thereby decoding reception data. M sequence (Maximum Length Code) or GOLD code is generally used as the spread codes. In the above coding, the number of the positive codes and the number of the negative codes are substantially equal to each other in the code sequence length, and thus code balance is established.
Further, the synchronous acquisition circuit is a circuit for accurately estimating the phase (code generation timing) of a spread code to perform the inverse spread processing on the reception signal, and it works to estimate the code generation timing of the spread code generated at the transmitter and the code generation timing of the spread code prepared at the receiver within a precision of one chip of the spread code, and start the operation of a spread code generator at the receiver at the above timing.
FIG. 7 is a schematic block diagram showing a conventional CDMA synchronous acquisition circuit. The synchronous acquisition circuit shown in FIG. 7 includes a reception antenna for receiving a transmission signal from a transmitter (not shown), a quasi-coherent detecting circuit 12 for converting the received signal to a base band signal, an A/D converter 13 for converting the base band signal to digital data, a correlator 14 for calculating a correlation value output from the digital data after the A/D conversion, a phase shift circuit 15 for shifting the code generation timing of the spread code by a fixed time, a memory 16 for accumulating the correlation value of the spread code by one period of the spread code, a signal level detecting circuit 17 for detecting the maximum correlation value level from the correlation value level which is accumulated over one period of the spread code in the memory 16, and a clock generating circuit 18 for generating clocks needed to each part of the circuits. The correlator 14 contains a multiplier 141, an integrating circuit 142 and a spread code generating circuit 143.
In this construction, an RF (Radio Frequency) signal which is received from the reception antenna 11 is converted to the base band signal in the quasi-coherent detecting circuit 12, converted to the digital signal in the A/D converter 13, and then input to the correlator 14. In the correlator 14, the spread code sequence output from the spread code generating circuit 143 is multiplied by the output signal of the A/D converter 13 every one-chip of the spread code by using the multiplier 141. The output of the multiplier 141 is input to the integrating circuit 142, and integrated over the length of the spread code sequence. The output of the integrating circuit 142 is set as a correlation value at a spread code generation timing of the spread code sequence. The output of the correlator 14 is accumulated in the memory 16.
After the correlation value is output from the correlator 14, the spread code generating circuit 143 is shifted in phase by a fixed time which is shorter than the chip rate of the spread code by the phase shift circuit 15, calculates a correlation value from the reception signal at the spread code generation timing in the same manner as described above, and the stores the correlation value in the memory 16. Accordingly, in the memory 16, the correlation value which is calculated over the phase timing within one chip of the spread code sequence is accumulated over one period. Subsequently, a reception delay position having the maximum correlation value level is selected from the correlation value level accumulated in the memory 16 by the signal level detecting circuit 17. By using the reception delay position, the reception signal is subjected to inverse spread processing in an inverse spread circuit (not shown) by using the spread code sequence generated from the reception delay position as a replica.
Next, the construction of a CDMA receiver containing a conventional DC (Direct Current) offset removing circuit will be described.
FIG. 8 is a schematic block diagram showing a CDMA receiver disclosed in Japanese Laid-open Patent Application No. Hei-2-47911. The receiver shown in FIG. 8 includes a reception antenna 11 for receiving a transmission signal from a transmitter (not shown), a quasi-coherent detecting circuit 12 for converting the reception signal to a base band signal, a capacitor 71 for removing DC offset components, an A/D converter 13 for converting to digital data the signal after the DC offset components are removed, a synchronous acquisition circuit 74 for calculating a correlation value for each phase timing of the spread code sequence with the digital data after the A/D conversion of the A/D converter to estimate the spread code generation timing having the maximum correlation value, an inverse spread code generating circuit 73 for generating an inverse spread code which is a replica of the spread code which is estimated by the synchronous acquisition circuit 74, an inverse spread circuit 72 for inversely spreading the digital data with an inverse spread code, and a clock generating circuit 18 for generating clocks necessary for each part of the device.
In the CDMA receiver thus constructed, the reception RF signal which is received from the reception antenna 11 is input to the quasi-coherent detecting circuit 12, converted to the base band signal and then output. The DC offset components of the base band signal are removed by the capacitor 71. The base band signal from which the DC offset components are removed is subjected to A/D conversion by the A/D converter 13, then the phase timing of the spread code having the maximum correlation value is estimated by the synchronous acquisition circuit 74, and then the digital signal after the A/D conversion is subjected to the inverse spread processing in the inverse spread circuit 72 by using as a replica the spread code generated at the reception delay position in the inverse spread code generating circuit 73.
FIG. 9 is a block diagram showing another construction of the CDMA receiver containing an DC offset removing circuit. The same reference numerals as those of FIG. 8 are represented by the reference numerals. The difference of the receiver of FIG. 9 from that of FIG. 8 resides in that a DC offset removing circuit for removing DC offset from the A/D-converted output signal 82 is provided, and the signal from which the DC offset is removed is subjected to the inverse spread processing.
In this construction, the reception RF signal which is received by the reception antenna 11 is input to the synchronization detecting circuit 12, converted to a base band signal and then output. The base band signal is input to the A/D converter 13 and converted to a digital signal. The digital signal 82 which is output from the A/D converter 13 is input to the DC offset removing circuit 81 to remove the DC offset components. By using the signal from which the DC offset components are removed, the phase timing of the spread code having the maximum correlation value is estimated by the synchronous acquisition circuit 74, and the digital signal after the DC offset is removed is subjected to the inverse spread processing in the inverse spread circuit 72 by using as a replica the spread code generated from the inverse spread code generating circuit 73 at the reception delay position.
FIG. 10 shows the internal construction of the DC offset removing circuit 81. In FIG. 10, the DC offset removing circuit 81 comprises a low-pass filter 92 for removing signal components other than the DC component, and an adder 91 for inverting the signal components thus removed and adding the inverted signal components to the signal 82.
In this construction, the base band signal 82 based on the digital signal output from the A/D converter 13 is input to the low-pass filter 92 through the adder 91. In the low-pass filter 92, the signal components other than the DC component are removed from the base band signal 82. At this time, the output signal of the low-pass filter 92 is set as an estimation value of the DC component, and the estimation value is inverted and input to the adder 91, whereby the signal from which the DC offset component is removed is output from the adder 91.
The above-described conventional technique has the following problems.
As a first problem, the conventional CDMA synchronous acquisition circuit shown in FIG. 7 has such a drawback that the DC offset components due to D/A conversion, A/D conversion and spread code unbalance are contained in the correlation value calculated by the correlator. Accordingly, an accurate correlation value level cannot be detected when the maximum correlation value is detected by using this correlation value to estimate the optimum spread code generating timing, and thus an erroneous phase position may be estimated as the maximum correlation value. Therefore, a reception error occurs, and thus reception quality is lowered.
As a second problem, the conventional CDMA receiver shown in FIG. 8 has such a drawback that the DC offset component due to the A/D converter cannot be removed from the digital data used in the synchronous acquisition circuit because the DC offset component is removed by the capacitor before the A/D conversion.
As a third problem, the convention CDMA receiver has such a drawback that when a correlation value is calculated on the digital data passed through the DC offset removing circuit by a correlator in the synchronous acquisition circuit, the DC offset cannot be accurately removed if the spread code varies on a symbol basis. Particularly when codes having an extremely long coding period are used and the spread codes are used on a symbol basis, the DC offset component which occurs in accordance with the code balance of the spread code used vary on a symbol basis, and thus the removal of the DC offset components is insufficient in the conventional DC offset removing circuit for removing DC offset components which are expected in advance. Further, there is also such a drawback that the power consumption of the DC offset removing circuit is large. This is because the DC offset components are removed from the signals at the stage before the synchronous acquisition circuit, and the clock corresponding to the chip rate of the spread code is needed to actuate the DC offset removing circuit, so that a semiconductor device which works at high speed and needs large power consumption is needed.